DFT for Low Power Design with Multiple Voltage Modes in DVFS

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DFT for Low Power Design with Multiple Voltage Modes in DVFS

DVFS, Dynamic Voltage and Frequency Scaling, has proven to be an efficient way to reduce SOC dynamic power. Below diagram illustrates the concept of DVFS. With CPU as an example, it can work in several active modes. In the high power mode, CPU needs to support high computation requirement and therefore needs to run at high clock rate or high frequency. In the low power mode, CPU only needs to support low complexity tasks and can just run at low clock rate. Adjusting clock rates itself already reduces power. On top of that, the voltage of the CPU module can also be reduced. The background knowledge is high clock rate requires high voltage to close timing and low clock rate can work in low voltage. Due to power=C*F*V*V, the power saving due to voltage drop is even higher than frequency drop.

There are several considerations of adopting DVFS. For example,

  1. How to combine DVFS with chip’s process corner and temperature condition?
  2. Does voltage adjust affect functionality? Voltage scaling could happen when chip is in active operation.
  3. The sequence of DVFS. For example, a core needs to request high voltage and wait for high voltage ready before increasing its clock rate.
  4. How long does it take to do DVFS? It depends on analog PMU design. Below diagram is an example showing how an internal PMU can speed up DVFS compared to an external PMU.

 

But function design of DVFS is only half of the story. This article focuses on the other half which is the DFT, Design for Test, consideration of DVFS. We will lay out some guidelines. They are critical and practical but often omitted for novice which leads to non-testable or bad-coverage DVFS design.

 

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