Multiple power domain methodology has been adopted widely in modern low power SOC design. In this post we briefly review how to handle DFT in multiple power domain design.
There is an interesting article, low power design for testability, about how to apply DFT to test power management circuitry and improve test and fault coverage during ATPG.
In this article, a power aware daisy chain methodology is introduced. “Daisy-chain implementation along with bypass multiplexers (1, 2, 3, and 4) and four different power domains (A, B, C, and D) is shown in Figure 2. As can be seen, bypass multiplexers allow testing of specific power domains in multi-Vdd environment. As an example, in a particular power mode, where power domains C and D are ON, while A and B are OFF, muxes 1 and 2 goes in bypass mode, while 3 and 4 are in pass-thru mode. This forms a scan chain between SI, 3, 4, and SO. The bypass multiplexers are placed on always-on power domain”
Below is a more detailed drawing showing how isolation is asserted on scan chain among power domains.
But most likely your DFT tool doesn’t support power aware scan chain stitching. DFT tool stitches scan chain based on clock domain. It stitches FFs in a clock domain together. It is possible one scan chain contains multiple sub-chains of different clock domains. But it is done properly by inserting hold FF in between. Therefore if multiple power domains also belong to different clock domains, scan chain per power domain is automatically achieved. But if multiple power domains belong to the same clock domain, this methodology won’t work. If DFT blindly assigns multiple power domains to multiple clock domains and omit the fact they belong to the same clock domain in functional mode, the valid paths between power domains won’t be timed and tested in DFT which leads to test coverage issue.
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