DFT Core Wrapper Cells from DFT Compiler and Logicvision

Make it to the Right and Larger Audience


DFT Core Wrapper Cells from DFT Compiler and Logicvision

Here we use Synopsys DFT compiler as an example to talk about how DFT wrapper cell or DFT isolation cell is used in ASIC core level DFT test. Then we briefly talk about Logicvision DFT isolation cells.

The following diagrams are from Synopsys DFT Compiler User Guide.

The core level DFT test is to allow functional core to be tested separately from other functional logics. Therefore we can test multiple cores in parallel and we can divide and conquer DFT issues such as coverage per core. It also eases IP design since IP core design team can make that IP core also a DFT core and deliver patterns with the core.


To facilitate above goal, the core needs to be wrapped or isolated from the outside world. All the core input pins need to have input wrapper cell and all the output pins need to have output wrapper cell. Input wrapper cell disconnects outside functional input, allows test pattern to be shifted in (into an FF inside wrapper cell) and then drive the core. Output wrapper cell needs to capture the core output, save the captured value into the FF inside wrapper cell, and then shift out through scan chain to observe.

Above is only half of the story since the goal is to test the core which is called INTEST mode in Synopsys DFT Compiler. Sometimes we want to test the outside logic which is the EXTEST mode. In this case, we do pretty much the opposite – input wrapper cell captures outside logic output and shifts out while output wrapper cell gets pattern shifts in and drives outside logic.

The following is wrapper cell WC_D1. It is used on both input and output side. cti is core test input. cto is core test output. cfi is core functional input. cfo is core functional output. shift_clk is scan chain shift clk. shift_en is shift mode enable. capture_en is capture mode enable.

One shortcoming of WC_D1 cell is the controlled output of the wrapper cell can toggle as data is shifted through the wrapper chain. This may trigger false operation on outside logic. To avoid this, we can use the following WC_D1_S cell. It adds a mux with two pins, safe_control and safe_value, to WC_D1 cell.

The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 1258 words, 9 images
Hardware Engineer
Author brief is empty



Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.


©2020  ValPont.com

Forgot your details?