Delay chain in DFT mode

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Delay chain in DFT mode

In design, we usually see delay chain logic in DFT mode. It may causes either unexpected mismatch and impact on timing signoff in DFT mode. The easy way to solve this is to gating them with dft mode signal, hence in STA APR guys won’t see these huge timing violation path with respect to delay chain under DFT mode.

 
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