Delay chain in DFT mode

Make it to the Right and Larger Audience


Delay chain in DFT mode

In design, we usually see delay chain logic in DFT mode. It may causes either unexpected mismatch and impact on timing signoff in DFT mode. The easy way to solve this is to gating them with dft mode signal, hence in STA APR guys won’t see these huge timing violation path with respect to delay chain under DFT mode.

Author brief is empty

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.



Forgot your details?