Debug Memory Read Issue with Timing Analysis and Experiment

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Debug Memory Read Issue with Timing Analysis and Experiment

In lab we have an issue that on some parts and under certain condition, the content read out of memory are wrong. We have three memories, ram_a/b/c, used for this functionality. Physically they locate adjacent to each other on chip. Issue is only observed on ram_b. Memory content is good since after issue happens that mem read is wrong, we let firmware to read the same location multiple times and then it is all good.


Suspect it is mem read timing issue. Run STA to report setup and hold margins for these three memories. Below table is the worst slack/margin for hold timing of each corner. This is UMC 16nm process. We check timing at six corners. FF/SS refers to fast or slow process. V070/V084 refers to voltage of 0.7v and 0.84v. t80/t-20 refers to temperature of 80C and -20C.


First, we notice for each memory it is the same path, one of address lines, has the worst slack across six corners. In fact, this address bit gives the worst slack for all three memories too.

Second, we notice ram_b has the smallest hold margin compared to the other two memories. This is in line with lab observation that issue only happens ram_b.

ram_a ram_b ram_c
ff_v070_t80 0.1812 0.1171 0.2488
ff_v070_t-20 0.2276 0.1564 0.2763
ff_v084_t80 0.0839 0.0406 0.1458
ff_v084_t-20 0.0962 0.0555 0.1444
ss_v070_t80 0.2731 0.1873 0.3328
ss_v070_t-20 0.3102 0.2358 0.3624

Taking a closer look of above table, we can see

  1. hold margin reduces from ss to ff.
  2. hold margin reduces from -20C to 80C.
  3. hold margin reduces from 0.7v to 0.84v.
  4. worst corner for hold is ff_v084_t80


We suspect ram_b has hold timing issue in lab and we would like to increase hold margin on ram_b. Since we can’t change ff/ss of a part and it is also difficult to change temperature (we don’t have temp chamber or hot/cold air gun handy), the only test seems left is to lower voltage.

This table shows when voltage decreases how hold margin improves. As can be seen, both data arrival time and data required time increases and the ratio is similar. This is because both data path delay and clock path delay are larger since cells are slower at lower voltage.

ff_v070_t080 ff_v084_t080 ratio
data arrival time 1.4393 1.105 1.302533937
clock network delay 1.3987 1.1345 1.23287792
clock reconvergence pessimism -0.3016 -0.2504 1.204472843
clock uncertainty 0.044 0.044 1
library hold time 0.0937 0.0783 1.196679438
data required time 1.2348 1.0064 1.226947536
statistical adjustment -0.0232 -0.0148 1.567567568
slack 0.1813 0.0838 2.163484487

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