Crystal safety margin test and crystal startup time reduction

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Crystal safety margin test and crystal startup time reduction

There are two common issues with usage of crystal. Crystal oscillation becomes unstable with the aging of crystal or environment such as surrounding temperature change. Crystal oscillation may take a long time to start and end up with a stable/acceptable state. I would like to share a good document about crystal usage from TI, MSP430 ™ 32-kHz Crystal Oscillators. Although it is a app note, the discussion is very generic. Not only these two issues are discussed but also other topics such as load capacitance vs osc frequency and crystal circuit board design considerations.

 

Negative resistance test is normally conducted to check crystal safety margin. With higher margin, crystal has a good chance to remain oscillation with aging and environment change. Rq is introduced in the crystal circuit as shown below. We adjust Rq and check if crystal can remain oscillation.

The maximum value of Rq that can keep crystal oscillation is called Rqmax. Define ESR as crystal’s effective serial resistance, safety factor (SF) can be specified as below:

We normally require SF>=5 for production quality.

Below is some more detail of how crystal ESR is defined. ESR can be normally found in crystal datasheet. Rqmax can be measured on test board.

 

So let’s say lab test shows SF is <5. To improve SF, we need to adjust the “inverter” cell which is most likely an op-amplifier in a chip. The op-amp can have several settings to adjust its bias, driving strength, etc. Adjust these settings can increase SF. In fact, op-amp setting can be pre-determined in simulation. Find crystal ESR value from crystal datasheet. Add above Rq=4*ESR and simulate if crystal circuit can oscillate at SF=5.

 

Some may argue crystal startup time may not be important at chip cold boot. This may be true. But crystal circuit current can be high. We normally shut down crystal when it is not needed to save battery power. So it can be seen crystal start time is critical when we need to turn it back on. If start time is long, we have to turn it on early and it means more time in high power mode.

 

TI app note mentions two ways to reduce start time, kick-start noise and high startup op-amp driving strength.

 

The app note further shows an assembly code for firmware to toggle an on-chip control bit to do above switching. Here it assumes firmware is running out of another crystal. But what if we are talking about the crystal which also drives processor which firmware runs on? This kick-start noise can be generate a hardware circuit. The hardware still needs a clock and this clock can be generated from a on-chip RC oscillator. Compared to crystal osc, RC osc has a big range of osc frequency which is normally not accurate enough for applications. But it is good enough to, ie, turn on crystal circuit.

 

The 2nd method to reduce start time is to use high driving strength setting for the op-amp. This normally reduces start time but also makes sure crystal has a good chance to osc from cold condition. Note that once oscillation is stable, we normally use low driving strength setting for op-amp for two reasons. One is to reduce current consumption. Current of high driving strength setting is high. 2nd is reliability issue. High driving strength can make crystal aging faster and eventually it may fail.

 

Here is the TI app note FYI.

 
Electrical Engineer
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1 Comment
  1. chieuluu 9 months ago
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    Nice

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