In “ARMv7-M Architecture Reference Manual”, it is specified ARMv7-M address map is as below. The first 0.5G space, with address below 0x2000_0000, is specified as Normal memory/device type.
But there is a potential concern that two AHB transactions may have their order reversed. For example, two write transactions to the same address may be reversed and obviously it will cause issue.
Let’s see where this concern comes from. We label two AHB transactions as A1 and A2 with A1 comes before A2. Below table is from above ARMv7-M manual and specifies if these two transaction order is maintained.
For Normal type memory, A1 and A2 transactions are just normal accesses. Out of above table, their order is NOT maintained! But if you have a Cortex-M system, likely you don’t see issue. Here is why.
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