We have been helping multiple customers successfully convert their SOC or FPGA projects into low power design. By low power design, we are not just lowering idle and sleep mode current but also active mode or dynamic current. This article is based on our years of experience on this subject. It should be the first article in this low power series you want to check out. Note here we talks about low power design at SOC level and not at system level. So the discussion should be applicable in a more general way.
You can purchase points of this author. You have 0 points and this post costs 2 points.