Consideration of Clock and Reset Handling in DFT

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Consideration of Clock and Reset Handling in DFT

In my two other posts, Asynchronorous Reset in DFT and RTL Changes for DFT Support, it is mentioned how to handle clock and reset for DFT purpose. Both need some RTL change and DFT flow won’t be able to fully handle it. But that approach has some limitation in dft testing performance. In addition RTL change for DFT purpose can be confusing for non-DFT guys and distract designers from focusing on the real functionality. Both can be improved with the new approach discussed in this post.

This post also discusses how to control clock gating ICG cell in dft test for both logic test (LBIST/ATPG) and memory test (MBIST).


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Highlights: 1043 words, 8 images
ASIC and Process Engineer
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  1. Frank 8 months ago


  2. Frank 8 months ago

    thanks for sharing!


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