A simple AHB connection is one master talks to one slave. Hready is from slave to master and used by slave to insert wait state. But in more advanced AHB bus design, we can see HREADY and HREADYOUT. AMBA doc says “slaves on the bus require HREADY as both an input and an ouput signal”. What does it mean?

Turns out HREADY/HREADYOUT pair kicks in when there is multiplexor in connection. In other words, one AHB master drives multiple AHB slaves. Each slave has a HREADYOUT and multiplexed HREADYOUT goes to master.

But is above connection good enough? Let’s see the issue. At one time, master starts transaction B to slave B. Then master sees HREADY=1. This is asserted by transaction A’s slave. So in next cycle, master not only starts transaction B’s data phase but also start transaction C’s address phase. Slave B deasserts HREADY and master will hold transaction B’s data phase. But at this cycle, slave C sees transaction C’s address phase. All good and in the next cycle slave C will do a write but write data is transaction B write data.

What goes wrong here?

 

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