ASIP stands for Application Specific Instruction-Set Processor. As introduced in Application-Specific Processors for High Throughput, Low Latency, and Flexible 5G Communication SoCs , ASIP poses to bridge the gap between highly optimized fixed-function hardware implementations and standard processor IP.
This post is a short step by step comparison of fixed to flexible hw approach, ASIP, and DSP approaches. We will see their boundaries are actually blurred. Hope this post helps you to choose the proper approach for your design.
Let’s start with a basic hw design. The only thing it does is to multiply two numbers. First we have DR1 and DR2 two data registers to store two multiplicands. Result is saved into another data register DR3. DR1/DR2 can be written by CPU and DR3 can be read out by CPU. For the control path, we have some control registers (CR) and a FSM to enable/disable the operation. The operation sequence of this module can be:
- CPU loads multiplicands into DR1/DR2.
- CPU kicks off operation by writing CR.
- FSM enables operation and result is saved into DR3
- CPU reads out DR3
- the kick off in step #2 does not have to be from CPU. Another hw module can generate a interrupt to trigger the operation.
- above assumes this module is an offline hw accelerator so DR1/DR2/DR3 are accessed by CPU. This module can also be in the middle of a data path and DR1/DR2/DR3 are connected to other hw modules. For example DR3 can be designed as a FIFO. When FIFO reaches certain level, it notifies the downstream module to read out some amount of data and start its processing.
Above design gets CPU involved quite a bit. Let’s say we want to offload CPU. We can put a DMA into this module. DMA can be triggered by FSM to load multiplicands from memory into DR1/DR2 and write DR3 back into memory.
DMA operations can be queued. We can further assign some kind of instruction memory to DMA. This instruction memory specifies a queue of memory locations for this module to operate on.
Above is a flexible hw design already. It bears some similarity to ASIP. If we design this module in ASIP, it can look like below. It has a instruction memormy which CPU needs to load instructions into it at first. Then once started, processor core will read instruction out of instruction memory and executes. As a result of execution, processor core can
- instruct Bus Master (BM) to load multiplicands from memory into DR1 and DR2
- do multiply operation
- instruct BM to write DR3 into memory
In step#1 and #2, memory locations are embedded in instructions. That’s it. A simple ASIP. By changing instructions, you can do a flexible multiplication.
But so far we haven’t touched the main benefit of ASIP yet.
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