Clock Tree Balancing

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Clock Tree Balancing

We would like to share one good slides about CTS, clock tree synthesis. Most articles online are shallow and only touch the basic concepts. This seminar tutorial from Synopsys talks about real issues seen in large and more realistic ASIC designs.


Inspired by this slides, we would like to make a couple of points.


First, the slides mentions CTS will try to balance flip-flops at different layers, may them be close to clock root or reside far away from clock root.

If this is true, it is a big concern that clock tree power can be way higher than necessary. Taking below SoC as an example, the whole system may belong to the same clock domain. If clock tree needs to balance skew of every FFs in one clock domain, it is very difficult to achieve. Lots of strong and therefore power hungry clock buffers will be inserted. But indeed why do we need to balance skew of FFs in TCP/IP and PWM modules? They don’t talk to each other or in other words there is no path between FFs in these two modules.


Fortunately it is not the case. When clock tree is built, CTS tool will analyze if need to balance FF skews. As a result of this process, FFs in a clock domain are not skew balanced but any valid path can meet timing and therefore the system can properly function.


Second, delay caused by non-CTS cells like clock divider may need to be compensated. Clock divider introduces extra delay on clock. This delay is normally independent of clock divide ratio. It is the same delay no matter divided by 2, by 4, or by others. But the direct feed-through path, or divide by one path, has different delay. This delay difference needs to be compensated. The slides shows a module called “Dividing clock delay equalizer” for this purpose. In fact modern CTS tool is capable of doing compensation automatically based on clock constraints. But lots of time designer needs to monitor how clock buffers are added to compensate this delay. The clock buffers may be added on leaf cells side while they should be added on clock divider side. Adding clock buffers on leaf cell sides can cause higher clock tree power since it means more buffers are added.




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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.


1 Comment
  1. patenpoker 11 months ago

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