SoC normally has on-chip PLLs to provide clock sources for digital and analog circuits. For DFT test, it is one of common practices to use GPIO to provide external test clock. But using PLL as DFT test clock is desired. First, GPIO generally can’t support high toggling rate. Lots of time it is not possible to provide hundreds of MHz or even GHz level clock externally. In this case internal clock source, PLL, is only option to support at speed test. Second, PLL is also used in normal functional mode. Using PLL as test clock is closer to real case since parts of func mode clock tree is also involved in test mode.
But to use PLL as test clock is not straightforward. Here is a common mistake.
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Good point for true at speed test