Case study: how to insert logic on cross hardmacro signal properly with power domain consideration

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Case study: how to insert logic on cross hardmacro signal properly with power domain consideration

In Case study: how an isolation cell can be falsely inserted and screw up your design, we discussed a case how to avoid a false isolation insertion. Related to this case, this article discusses how to insert logic on cross hardmacro signal properly.

 

We have two modules M2a and M2b and both are in PD_M2 power domain. A M2a to M2b signal goes through PD_M1 power domain. PD_M1 is less on than PD_M2 which means it is possible PD_M1 is off and PD_M2 is on and we need M2a to M2b signal still functions properly.

Now Let’s look at the issue we want to discuss. Assume by design we need BE to insert delay cells for whatever reasons such as fix timing. If we add delay cells as below, it doesn’t work.

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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.
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