Case Study: How Memory Consumes High Leakage in Sleep Mode

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Case Study: How Memory Consumes High Leakage in Sleep Mode

In a chip project low power simulation all look good. But when chip comes back we see memory current is way too high in sleep mode. Here is the simplified memory architecture. It consists of peripheral, peripheral nwell, memory array, and array nwell. Perif and perif nwell shares the same memory supply input pin, PS_mp (PowerSupply_mp). Array and array nwell shares the same supply input pin, PS_ma. Outside memory PS_mp and PS_ma are connected together to PS_mem. PS_ma and PS_mp are wired together because array and peripheral are of the same voltage level and this memory has internal power switches to be able to shut down perif and array independently. Mem perif power switch is controlled by mp_pu (mp_powerup) and array is by ma_pu.

In active mode, both array and perif are on. In sleep mode, perif is shut down and array can be kept on to save content. Perif nwell and array nwell can be on all the time. Since perif can be off while array is on, there are isolation cells inside memory for signals coming from perif to array. These iso cells are controlled by iso_arr.

On bench when chip enters sleep mode, ideally mp_pu=0 to shut down perif, ma_pu=1 to retain array, and iso_arr=1 to isolate.  But we observe high leakage on PS_mem. Next we’ll discuss two issues and how each of them can cause this high leakage.


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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.


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