Case study: how an isolation cell can be falsely inserted and screw up your design

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Case study: how an isolation cell can be falsely inserted and screw up your design

 

Low power design is common in modern SOC designs. The design is partitioned in several power domains. When a signal from a power off domain drives a load in a power on domain, isolation needs to be inserted. But sometimes an isolation cell may be falsely inserted and makes logic malfunction.

 

Here is an example how it can happen. There are two modules, M2a and M2b, and both are in PD_M2 power domain. M2a and M2b are instantiated in a top module which is in PD_M1 power domain. A signal called hready goes from M2a to M2b. When PD_M2 is up and PD_M1 is down, we would like M2a and M2b to continue function which means hready to continue toggling regardless that PD_M1 is powered down.

 

 

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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.
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