Cadence HLS Stratus IDE Basic: How to Use the Example FIR Project

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Cadence HLS Stratus IDE Basic: How to Use the Example FIR Project

Intro

High level synthesis (HLS) has gained lots of popularity in recent years. It allows, for example, system team to generate RTL based on their system code. Therefore it eliminates big efforts of RTL design and verification.

There are several stable HLS tools on market. One of the popular tools is Xilinx HLS which is integrated into Xilinx ISE/Vivado IDE. Stratus is a new offering from Cadence which replaces old Cynthesizer tool.

Here we use Cadence FIR filter example project to show how Stratus works.

 

First, in your linux terminal, type “stratus_ide&”. It will launch Status IDE. The welcome window is as below.

 

There are several example projects you can use to get familiar with Stratus. In this post let’s pick Ex 4 Simple FIR Filer. Click on it. A window pops up.

It is saying the example project location is write only. It asks you to specify your working directory so the tool can copy this project over there.

Once you specify your working dir, files are copied and Stratus window shows header files, source files, Makefile, and project.tcl of this project.

Click on fir.cc, it will show in edit window. The help window will show a short description of how to use this example.

This example contains a very simple FIR filter. It demonstrates how trivial it is to get multiple RTL implementations of the FIR from a single SystemC model of the filter.

First, we can do behavioral simulation. Behavioral simulation is usually run as you are developing or changing the behavioral code. There is no RTL code involved and these models typically simulate very quickly. The project, as delivered, already contains a number of simulation configurations. This makes running the simulations simple.

  • Select the behavioral simulation configuration (“B”) in the Stratus Project Tree.
  • Press the RUN button (Green triangle in the bottom left corner).
  • Once complete, go to “Analysis” mode to review the results.

When behavioral simulation is done, in Job Trace you should see below. You should see similar if click on “Analysis” mode button.

And in your simple_fir/bdw_work/sims/B directory (note everything under bdw_work is tool generated), you should see systemc.vcd. You can check signal timing using this vcd file.

You may be interested to know what ‘B” is about. It is defined in project.tcl to represent behavioral simulation.

 

Next let’s try high level synthesis. This example has several HLS configurations pre-configured in project.tcl.

It is also shown in project window. Each configuration uses a different set of command-line flags and synthesis directives and will produce a different RTL implementation.

 

To run synthesis, select the appropriate synthesis configuration for the “fir” module and press the green RUN button. Let’s select “ASIC” one as an example.  After HLS is done, click “Analysis” to see the result.

The “tmp_dir” or the working dir for HLS is bdw_work/modules/fir/ASIC. To browse files, you can select “File System” and browse into tmp_dir.

Three important generated files are fir_rtl.cc, fir_rtl.h, and fir_rtl.v. Fir_rtl.cc is RTL captured in SystemC.   It has clock, reset, and uses SC_METHOD with clock. So it is RTL in cycle-accurate SystemC.

fir_rtl.v is just RTL written in normal Verilog.

With RTL available, let’s check RTL waveform. Project.tcl defines RTL simulation configurations for each HLS strategy.

Since we use “ASIC” for HLS in above, we need to select “ASIC_V” for RTL simulation. With “ASIC_V” selected, click on “run” button will kick off RTL sim. Again, enter “Analysis” mode when simulation is done. It shows something like

The working dir for ASIC_V sim is bdw_work/sims/ASIC_V. You can see verilog.vcd file in this dir once sim is done. You can use whatever simulation tool to view the waveform.

 

In Stratus IDE, you can continue with RTL synthesis to generate gate level netlist, do PnR, to analyze area, power, etc. This is important to get early design area/power estimation.

RTL logic synthesis is configured in project.tcl too.

 

 
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