Buffer Management and Data Transfer between Primary and 2nd Systems

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Buffer Management and Data Transfer between Primary and 2nd Systems

I wrote a blog titled Technical Brief of Two Qualcomm Patents that Apple found infringed . One of topics discussed is how to move boot image from primary processor system to the secondary processor system. I got PM asking about how normal mode data is transferred between two systems. This blog tends to address this question with a simple data buffer management design.

First let’s see how we move data from primary system to secondary system which is P2S. On the primary system side we can have a Data Segment Header (DSH) FIFO. FIFO entries are data seg headers which are of fixed word length. It can specify ID, series #, and most important of all a pointer to a data segment in pri system memory and the length of this data segment. Next we will see how this design works.

 

To transfer data fr P2H direction, here are the steps:

  1. primary processor first writes data into its system memory. Then it updates P2S DSH FIFO with an entry specifying the starting address and length of this data segment. Pri proc also needs to update wr_ptr, FIFO write pointer, due to new entry is entered.
  2. Pri processor sends an interrupt to 2nd processor
  3. 2nd processor reads P2S DSH FIFO and wr_ptr to grab the entries for the new data segment
  4. 2nd processor parses fetched DSH entries. Either it can read pri system mem directly or it can set up its DMA engine which will in turn move data from 1st system mem to 2nd system mem.
  5. 2nd processor updates rd_ptr, FIFO read pointer, and sends an interrupt on pri processor.

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