At-speed DFT test is critical to ensure chip free of timing issue due to design, timing closure, and manufacture issues. At speed test means on ATE tester the circuit is tested at the functional clock rate. This article is a basic introduction of how this is done in DFT design.
Below is a typical jtag tap controller hook up. Lbist controller is one of those DRs (data registers). Lbist controls scan chain during at speed test.
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In shift they may be the same slow scan clock while in at speed capture they may come from different OCC which runs at different frequency. If the ATPG does not setting any clock restriction they may be pulsed during the capture stage, hence if the have crosstalk paths your must deal with their timing, instead they can pulses togetther
Thanks. Can anyone answer my question
http://www.valpont.com/groups/research-and-design/asic-and-fpga/forum/topic/stitch-two-scan-chains-of-different-clock-domains-make-timing-closure-worse/#post-13728
Glad to realize there is both at speed shift and at speed capture.