Basic Introduction of Modern SOC Reset Generation

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Basic Introduction of Modern SOC Reset Generation

¬†has an interesting article, Some Discussion about MCU Resets. It talks about POR reset and LVD reset (low voltage reset) that are needed to make sure chip logic doesn’t work under voltage or with unstable clock. To achieve it, external reset generation chip such as MC34064 is employed. Reset delay is introduced by an analog RC charging/delay circuit. For details, reader can take a look of that article first.

This is a little old school. In today’s semiconductor industry, with the pressure to lower PCB BOM cost, digital chip vendors are integrating more and more functionalities into the chip. It includes POR reset and low voltage protection circuit.

Here we briefly talk about reset generation in a typical SOC. Below is a general block diagram.


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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.
1 Comment
  1. Ltremblay 5 years ago

    Great reading for soc top level design. You may not know a simple reset can be so necessarily complicated until you read it. Yes, it is related to bootup, clock, and power. I think low power (sleep mode) introduced reset issue is not even introduced.


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