Asynchronously Move Data Between Two Modules which Reside Far Away on Die?

Make it to the Right and Larger Audience

Blog/Press Release

Asynchronously Move Data Between Two Modules which Reside Far Away on Die?

I know the title sounds weird. But bear with me. Later you will see it is actually a common issue faced in SOC design.


Let’s say we have two modules, module a and module b. Each uses its own clock, clk_a and clk_b. Module a needs to send data to module b.

So it is a typical cross clock domain issue. One way is to send data asynchronously as shown in below. There is NO clock between two modules. Data and controls in between are all asynchronous. On module b side, an async interface module is needed to correctly sample data and put it in clk_b domain.

A more common way is to send data synchronously as shown in below two diagrams. Async interface is placed either on clk_a domain side or on clk_b domain side. There is a clock, clk_a or clk_b, running between two modules. Data and controls are synchronous to this clock.

At the first sight, moving data asynchronously is better. All signals across two modules are asynchronous so there is no need to close timing. But as explained in below, this way is much less adopted due to the low throughput. Moving data synchronously can achieve the high throughput and is therefore commonly adopted. But here is an issue. If two modules are physically resided close to each other on die, it is good to follow this way. But if they are far away from each other, closing timing on these synchronous signals can be painful, especially if the data are of high data rate. Is it possible to keep the high throughput while keeping all signals asynchronous?


The following is author subscription content.
To gain access you can subscribe to this author's posts at Subscription of SD-RTL-DGN Posts. Subscription is valid for three months.
Highlights: 1498 words, 8 images
Profile Photo
We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.



Forgot your details?