Whether to use asynchronous reset or synchronous reset is more of a topic on logic design side. If synchronous reset scheme is chose, DFT side is straightforward. Synchronous reset is treated just like a normal function connection. DFT does not need to do anything special. Indeed DFT doesn’t need to know that particular signal is synchronous reset or of some other function. But DFT handling of asynchronous demands some consideration.
There is a good blog site about Design for Test. In Part 28, it says “It is strongly recommended to avoid asynchronous resets in the design.” In fact, from what I observe, more chip projects use asynchronous reset these days. Let’s discuss how to handle async reset in DFT.
The following is a typical async reset usage case. An async reset, async_rstn, comes in and it first needs to be synchronized to the target clock domain. The synchronizer is achieved with the typical two flip-flop scheme. Synchronized async reset then drives async reset pin of flip-flops of the target clock domain.
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