Memory power is a big contributor to overall asic power in both active and sleep modes. There are several commonly adopted low power design techniques for memory. They are briefly touched here. Let me use Synopsys SiWare memory as an example. Its public available document can be found online at UMC 40nm SiWare™ MEMORY COMPILER POWER MODES.
First, memory can be single rail or split rail. Memory consists of peripheral and array. Peripheral is digital logic and array is the bit cells. Single rail means peripheral and array share the same supply input. Split rail means peripheral and array each has a dedicated supply input. Split rail is more complex but it can support peripheral and array to run at different voltages. In some process nodes, memory bit cells can run at lower voltage than standard cell based digital logic. While in some other process nodes, memory bit cells need to run at higher voltage. Either way, split rail allows two different voltages for peripheral and array. If single rail is used, the higher voltage has to drive both peripheral and array which leads to higher power consumption.
Second, memory can have several power modes. For Synopsys Siware memory, they are normal mode, light sleep (LS) mode, deep sleep (DS) mode, and shut down (SD) mode.
In LS mode, memory array is powered on and content is kept. Part of peripheral is powered on too but the left of peripheral is shut down. Compare to normal mode leakage, LS leakage is smaller due to partial peripheral shut down. Memory output pins are properly driven and maintain their last states, aka not x in simulation. Note this mode is also commonly called memory standby mode.
In DS mode, peripheral is totally shut down but array is kept on. Memory content is kept. Peripheral to array signals need to be isolated. This can be achieved by asserting memory isolation pin before put memory into DS mode. Memory outputs are held low.
In SD mode, both peripheral and array are shut down. Memory outputs are held low.
Third, in LS and DS mode, since there is no write or read access to memory array, array can be powered by a lower voltage to cut leakage. Obviously this needs split rail configuration. The high to low voltage switching can happen inside memory or outside memory.
Forth, when LS/DS/SD are asserted or de-asserted, is it required to meet setup/hold timing relative to memory clock? Below is from SiWare doc.
It is confusing. Generally timing requirement needs to meet for LS/DS/SD. But there is a special case. If memory clock is idle and parked at low, if LS/DS/SD are asserted or asserted during this time, does it work? Answer is yes. First, setup and hold can be met. Think of the case that clock still toggles but is very very slow. You can see setup and hold can be met. Second, memory can get into the corresponding low power mode. In addition, the same is true that memory clock is idle and parked at high.