ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating

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ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating

UMC 40nm SiWare™ MEMORY COMPILER POWER MODES also has a good introduction of when to enable standby (or light sleep) mode. This is because although standby mode has lower leakage, in and out of standby can consume some extra energy. So there is a break even point.

This is how break-even point is calculated.

Normal mode leakage and standby mode leakage can be found in liberty file or lib file generated by memory compiler.

The extra energy consumed in and out of standby is based on some datasheet numbers.

Another way to find this number is from liberty file. Check rise_power and fall_power at !cs condition since we normally assert standby when memory is not selected for active transactions. Note below ME is memory enable pin. It is also cs, chip select.


As for how to assert LS, it is discussed in my other post.


Unlike deep sleep (DS) and shut down (SD) which takes longer time to exit from the low power modes, light sleep (LS) entering and exiting is much faster. Therefore in lots of memory design it is allowed to dynamically enable and disable LS based on if there is a read/write transaction. LS exiting still takes one or multiple clock cycles which needs to be considered as access latency.


The next question is if we can get a memory low power mode which is even faster than LS to get out? If we gate off memory clock when memory is not used, does it save some power? clock gating can be achieved without latency sacrifice. The answer depends on your particular memory design. Again, this information can be found in memory liberty file. When memory is not enabled, clk rise_power() and fall_power() can be used to calculate how much power is consumed by mem clock pin toggling.



The result depends on clock rate. But most of time the extra power memory consumed due to clock toggling is much less than memory static leakage. So mem clock gating is normally not used. But sometimes we do see mem clock gating in some design. The fact is this clock gating is not intended for memory but instead intended to gate off clock on clock distribution network. In RTL, a clock connection is just a wire. On silicon, a clock connection may have many clock buffers. These clock buffers can consume quite a bit power. So gating off clock connection does make sense. But the gating cell location is important. If it is close to memory, it doesn’t help much since most clock connection is not gated off. We need to place it close to the root of clock connection.



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  1. chieuluu 1 year ago


  2. chieuluu 1 year ago



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