ASIC Interview Questions at A****

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ASIC Interview Questions at A****

Went to A**** at bay area to interview an ASIC design and integration engineer position recently. Here are some interview questions I can recall.

 

Q: how to design a circuit to calculate the average of 4 samples?

Just 3 delay FFs, sum of the outputs together, and then left shift by two (equivalent to divide by 4).

Q: how to design a circuit to calculate the average of 2048 samples?

2047 FFs? But sounds there could be a better way to reduce # of FFs used? Not sure.

 

Q: let’s say you have a FF output that drives tons of load and therefore is too slow to close timing. How to improve it?

Backend adds strong buffers on the fanout? The answer they are looking for is to duplicate the driving FF so each FF only drives a small # of loads.

 

Q: there is a binary sequence coming in. How to design a FSM to tell if 0 to 1 transition is more than 1 to 0 transition?

The key here is it is not to detect if # of 1’s is more than # of 0’s. Otherwise you will need to counter to count the difference of 1’s and 0’s. There will NOT be consecutive two 0 to 1 or 1 to 0 transitions.

 

Q: how to we specify asynchronous reset timing in timing constraint?

async reset needs to synchronized to clock. so it is a single cycle path.

 

Q: what is difference of ARM Cortex-M, Cortex-A, and Cortex-R processors?

big question. Check arm documents.

 

Q: how PCIe handles flow control?

Token based. Check pcie document.

 

Q: let’s say there is a FIFO. On the write side, the peak rate is 90 words per 100 cycles. On the read side, the peak rate is 9 words per 10 cycles. What is min depth of FIFO so it won’t overflow?

Consider the best case of write (write as fast as possible) and the worst case of read (read as slow as possible), the FIFO size is 9.

 

Q: how to improve AXI throughput?

Use outstanding transactions.

 

Q: if you suspect chip has setup timing issue, how do you prove that is case? Does this approach work for hold violation?

Lower clock rate, if works, it is likely setup timing issue. Doesn’t work for hold violation.

 

Q: What is the most challenging task you’ve faced and how did you resolve it?

 

 

 
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1 Comment
  1. chieuluu 1 year ago
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    Good article

    5

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