ASIC Die Size Estimation Due to Change of Process

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ASIC Die Size Estimation Due to Change of Process

Die size estimation is critical for upper management to evaluate a chip’s cost and project its performance in market.  When a chip stays in the same process node, it is relatively easier to estimate die size adder/subtractor for new features to be added and existing features to be removed. If a new feature is already designed, it is better to go through synthesis and P&R process to get a more accurate estimation. Otherwise designers can use existing similar design to estimate.

Let’s see how we can estimate die size when process node is changed. We are going to use the example design from iSine.



In this xls we show two ways to estimate 0.18um die size from 0.35um die size. We first need to split design into four parts

  1. logic gates which include flip-flops and combinational cells.
  2. Analog IP and OTP hard macros. This includes PLL, ADC/DAC, etc.
  3. IO pads
  4. Memories. In iSine’s mixed signal design example memory is not mentioned. But most likely memory is a big contributor to a chip’s area. Memories can include sram, RF (register file), ROM, etc.

The 1st way is to use scaling factor to scale all four parts. Scaling factors are 0.25 for logic gates, 0.8 for analog/otp, 0.4 for pads, and 0.5 for memories. So scaling factors are different which is why we need to split design into four parts. 0.18um “estimate area” is just 0.35um area times the corresponding scaling factor. For example, in xls, E5=C5 * D5. But this is not the final area. It is just area of cells and macros and does not include the overhead due to routing, dft, power/ground mesh network, etc. To take overhead into consideration, we can use utilization ratio. Final or real area is “estimated area” divided by utilization ratio. For example, in xls, G5=E5/F5.

Scaling factors normally come from library team, foundry, and IP design team. Utilization ratio is based on backend team’s experience. For example. routing overhead for std cell gates and FFs is high so utilization ratio for  logic gates is low. On the contrary, overhead for analog IPs and memories are low so their utilization ratio are high.



The 2nd way is actually a special case of the 1st way. Lots of time IP team already starts analog IP and memory design in new process. They can provide more accurate area for these macros and no scaling is needed.  Foundry’s reference library can be another good source for analog IP and memory die size in new process.


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