Inspired by an interesting slides about Jtag IEEE 1149.7 from Stephen Lau of TI (included in below), here we briefly talk about arm Jtag and DFT Jtag, as well as latest arm SWD and 1149.7. They are commonly seen in a typical ASIC design.
Today’s ASIC normally has an arm processor embedded in it. Therefore arm Jtag is needed to connect to external ICE debugger for firmware development, debug, and test. The following diagram comes from Arm Dap-lite specification.
Debug Access Port (DAP) contains the following components:
serial wire Jtag debug port (SWJ-DP)
APB access port (APB-AP)
APB multiplexor (APB-Mux)
On one side, SWJ-DP interfaces to Jtag pins directly. On the other side, debug APB is connected to arm processor debug APB port, which is connected to an APB slave resided inside arm processor core. APB-AP basically converts Jtag control into APB control and the APB master inside APB-AP can drive debug APB port and therefore accesses arm processor core. Debug APB can also be driven by “system access” APB. This one is optional and lots of times you can connect it to an APB master on your AXI/AHB bus. (Note for details, please check DAP-lite specification directly: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0316d/DDI0316D_dap_lite_trm.pdf )
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