ARM CoreSight for Cortex Processor Based SoC

Make it to the Right and Larger Audience

Blog

ARM CoreSight for Cortex Processor Based SoC

CoreSight is ARM debug suite and provides debug access to Cortex processor itself and the surrounding ARM subsystem. I tend to address some basic questions of CoreSight in this short post. Questions covered are:

  1. How are CoreSight components used in a typical ARM Cortex processor?
  2. What is difference between ITM, ETM, HTM, STM?
  3. How user can access trace information coming out of ITM/ETM/HTM/STM?
  4. What does TM trace data look like and how to interpret data?
  5. How does access port (AP) work?

Feel free to leave a question and comment.

 

Q1: In general, how are CoreSight components used in a typical Cortex processor?

Taking Cortex-M4 as an example, Serial-Wire (SW) or Jtag first accesses SW/JTAG Debug Port (DP). DP then accesses AHB Access Port (AP). AHB AP output port is a typical AHB master port and it talks to a bus matrix, aka AHB interconnect, inside CM4 core. This Bus Matrix has a APB master port and it is used to access various debug modules such as CoreSight ROM table, ETM, ITM, and TPIU through PPB APB bus. Note this PPB APB is just debug control path. Debug data path is those paths between bus matrix and ITM, between CM4 and ETM, between ITM and TPIU, etc.

The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 817 words, 4 images
 
Author brief is empty
1 Comment
  1. chieuluu 1 year ago
    0
    -0

    Good article

    5

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2021  ValPont.com

Forgot your details?