An Introduction to Synopsys BSD Compiler Insertion and Verification

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An Introduction to Synopsys BSD Compiler Insertion and Verification

This articles presents a basic introduction of Synopsys BSD compiler tool. BSD compiler supports boundary scan insertion flow and verification flow to insert JTAG Boundary Scan logic into functional design and verify it against 1149.1 standard and generate scan patterns as well as BSDL file.


In insertion flow, BSD compiler takes in functional design and tcl file which specifies BSDC configuration, constraints, and commands. BSDC then previews design and inserts BSD logics, TAP controller and BSR (Boundary Scan Registers), and generate netlist.
Before run the flow, design needs to meet the following requirements:

Prepare a top-level design and core design as show below. Top-level design should have functional I/O pad cells instantiated for all the ports. Top level should also properly connect I/O signals to core design. Leave JTAG I/O signals for TAP controller unconnected. The core design can be blackbox. Top and core design can be either RTL or gate-level netlist.



Next we need to prepare insertion tcl file.
1. define all the TAP ports:

set_dft_signal-view spec -type TDI -port tdi
set_dft_signal-view spec -type TDO -port tdo
set_dft_signal-view spec -type TCK -port tck
set_dft_signal-view spec -type TMS -port tms
set_dft_signal-view spec -type TRST -port trst_n

(Note use “-view spec” in insertion flow and “-view existing” in verfication flow)

2. configure TRST or POR (Power-ON Reset) so they can initialize TAP.

set_bsd_configuration -asynchronous_reset false
set_bsd_power_up_reset–cell_namePUR_cell –reset_pin_nameZ –active high –delay 100

3. Define compliance and linkage pins. For example, use below to define compliance enable signals, TEST_MODE and RESETN. (Both are 1 for TAP to function).
set_bsd_compliance -name P1 -pattern {TEST_MODE 1 RESETN 1}
Use below to identify linkage ports that should not have BSR (Boundary Scan Register) added:
set_bsd_linkage_port-port_list[list VDD VSS]

4. Define boundary scan configuration
-style asynchronous   \# TCK routing
-instruction_encodingone-hot  \# 1 inst per IR bit
-ir_width4    \# 4 bit IR Reg
-asynchronous_resettrue  \# TAP TRST reset
-control_cell_max_fanout3  \# 1 CTRL cell:3 pads
-std {ieee1149.1_2001}   \# 1149.6_2003 ACJTAG
-check_pad_designsall   # Validate Pad model

Most of above are default. In attached example, it is as simple as:
set_bsd_configuration -ir_width 4

5. define BSD intructions. Here is the command format:

-view <spec | existing_dft>  #spec for insertion flow
-code opcode_value  #instruction code
-register register_name  #Bypass, Boundary, UTDR
-input_clock_condition< PI | TCK >  #Default TCK
-output_condition< BSR | HIGHZ | NONE > #Default NONE
-capture_value<capture_vale>   #IDCODE and USERCODE
-private     #Not in BSDL file
-high inst_internal_pin_list  #Instance-enable high
-low inst_internal_pin_list  #Instance-enable low
-internal_scaninternal_scan_test #For SCAN_TEST instr

where input_clock_condition is the input clock signal to functional logic (your core) and output_condition is how functional outputs are driven during instruction.

The following four commands need to be always defined.
set_bsd_instruction -view spec [list EXTEST]  -code [list 0001] -reg BOUNDARY
set_bsd_instruction -view spec [list SAMPLE]  -code [list 0100] -reg BOUNDARY
set_bsd_instruction -view spec [list PRELOAD] -code [list 0100] -reg BOUNDARY
set_bsd_instruction -view spec [list BYPASS]  -code [list 1111] -reg BYPASS

User can define the following optional instructions:

set_bsd_instruction–view spec [list CLAMP] -code [list 1000] -reg BOUNDARY
set_bsd_instruction–view spec [list INTEST] -code [list 1001] -reg BOUNDARY -input_clock_conditionTCK
set_bsd_instruction–view spec [list HIGHZ] -code [list 1110] -reg BOUNDARY

Optional IDCODE to identify device code:
set_bsd_instruction[list IDCODE] -code [list 0011] -capture_value{32’b01} –reg DEVICE_ID

Optional USERCODE for user-programmable identificaton code:
set_bsd_instruction[list USERCODE] -code [list 1011] -capture_value{32’b01} –reg DEVICE_ID
6. Configure User-Defined Data Registers (UTDR). UTDR is optional.

Define UTDR and TAP interface signals:
set_dft_signal-type tdi -hookup_pin {core/tdi}
set_dft_signal-type tdo -hookup_pin {core/tdo}
set_dft_signal-type bsd_shift_en -hookup_pin {core/shift_en}
set_dft_signal-type capture_clk -hookup_pin {core/clk}
set_dft_signal-type bsd_reset -hookup_pin {core/reset}

Define UTDR itself:
set_scan_pathMY_REG -class bsd-view spec –hookup {core/tdicore/tdocore/shift_encore/clk} –exact_length10

Define user instruction to access UTDR:
set_bsd_instructionmy_instr-code {1010} -regMY_REG

7. Define pin order.
By default, pin order is derived from netlist in alpha-numerical order. User can use pin ma file to override it:
read_pin_map pin_map.txt
user can use set_scan_path command to fine tune pin order:
set_scan_pathboundary –class bsd -ordered_elements[list port1 enable1 …]

8. Enable BSD insertion
set_dft_configuration -bsd enable -scan disable

9. Run Preview
preview_dft -bsd all

Preview checks and reports tap ports connection, instruction, BSR, pads, pin order, etc. See attached log file for detailed report.

10. Insert BSD including design compile

Note mapping and optimication is done automatically after BD insertion. No need to run compile.

11. Check results and write out BSD inserted netlist and ddc file.

#Compliance checking
check_bsd -verbose
#Generate bsdl file
write_bsdl -out TOP_bsd.bsdl
#Generate bsd patterns
create_bsd_patterns -type all
write_test -format stil_testbench -output bsd_patterns
#write out jtag-inserted netlist
write -format ddc -hierarchy -output TOP_bsd.ddc
change_names -rules verilog -hier
write -format verilog -hierarchy -output TOP_bsd.v

The output design should have tap controller as well as BSRs inserted as below:

Next talk about BSD verification flow, which is actually already included in the last step of insertion flow.

1. check compliance with IEEE 1149.1
check_bsd -verbose

this compliance check simulates tap controller, IR register, bypass register, boundary-scan register, user test data register, in/out ports, and all instructions.

2. create JTAG testbench
first create functional test patterns:
create_bsd_patterns-output [ test_program_name] -effort [low | medium | high ] -type [all | functional | dc_parametric| leakage | tap_controller| tdr | bsr| reset ]

Next write out testbench:
write_test-format [ stil| stil_testbench| verilog| wgl_serial]

Generate BSDL (Boundary Scan Description Language) file:
write_bsdl -naming_check [ VHDL | BSDL | none ] -output [file_name]

You can see attachment for a simple example. It contains three folders.

1. design_data folder, contains top and core rtl as well as pin map file.
2. bsdc_insertion_flow folder, contains insertion tcl as well as output files.
3. bsdc_verification_flow folder, contains verification tcl as well as outputs.


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