An Example yet Practical PLL BEH Model for ASIC Integration and Simulation

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An Example yet Practical PLL BEH Model for ASIC Integration and Simulation

This short tutorial is to show junior ASIC design and verification engineers or EE students how to simulate PLL in an ASIC project.



Above is a typical PLL architecture and it is used as an example PLL in this tutorial. The analog core consists of PFD (phase frequency difference detection), CP (charge pump which translates PF difference to charging current to control VCO freq), filter (lowpass filter), and VCO. PFD takes in two inputs, reference clk divided by a programmable value (refClk_divN[7:0]) and VCO output clock divided by another programmable value (pllFB_divN[7:0]). There are multiple output clocks which are derived from VCO output and each has a independent divider.

In analog design, PFD and VCO each have an operating range. In our example, PFD is assumed to operate from 4 to 8MHz and the nominal is 6MHz. VCO is assumed to operate from 200 to 400MHz and the nominal is 300MHz.

Therefore, one application case is refClk is 4.5MHz, VCO output is 288MHz, refClk_divN=1, and pllFB_divN=64 (so 288/64=4.5). Just anther example. It can be refClk is 24MHz, VCO output is still 288MHz, refClk_divN=4 (so 24/5=4.8Mhz which is within PFD range), and pllFB_divN=64 (so 288/60=4.8)

Other input signals are:
rst_n:  active low reset signal.
sleep_n: active low. when active, pll is in sleep mode to save pwr and no clk out.
forceBypass: when high, PLL analog core is bypassed and divided refclk goes to VCO output directly (PLL digital part still functions so dividers are not bypassed).

Other output signals are:
pllLock: active high indicating PLL is in lock. Normally this signal comes from PFD block and is asserted when PFD sees alignment for successive tens of PFD clocks and deasserted otherwise.
sysrst_n: this signal follows pllLock and is optional. It can be used to reset digital logics and idea is if clock is not stable (not locked) digital logics should be in reset state. It is up to chip integrator how to use it.
When analog team delivers a PLL core to ASIC digital team for integration, the delivery normally contains GDS file (layout),LEF file (for floorplanning/etc), lib file (for BE timing analysis), and some simulation model in Verilog or VHDL.

1. Simulation model IO signals need to match those in lib, lef, and gds file otherwise BE side will flag error. Therefore they need to be properly connected at RTL level. Some pins can be just tie high or tie low. An example is supply and ground pins. If design flow support UPF, power and ground pins are not actually in verilog model.

2. From simulation point of view, lots of time our simulation goal is to check digital logic functionality. In this case, we can even bypass PLL beh model and just use forever loop to generate PLL output clock. This can speed up your simulation.


3. However, if the simulation goal is to check the control and timing of PLL (remember PLL has control inputs for programmable divider values and reset/sleep/bypass control inputs and pllLock and sysrst_n control outputs) or to simulate chip behavior at bootup or sleep entry/exit, we need to use PLL beh model delivered by analog group to include PLL control and timing.

4. PLL beh model delivered needs to model PLL reset beh, start/stop timing and sequence, and its response to divider value controls. In our example, PLL settling time can be controlled by verification engineer. It is normally a large value but to speed up simulation it can be set small in certain simulation.

5. Note normally PLL beh model delivered by analog group doesn’t fully or 100% accurately model PLL beh. For example:
5.1 clock jitter is normally not modeled in verilog model.
5.2 we mentioned our example PLL PFD and VCO have operating range. If out of range,our example PLL model can detect it and make outputs idle. This is hardly the real case. First, PLL out-of-range beh is more soft than hard which means PLL may still function when it is out of range and even if it malfunctions its output is not just idle and some outputs may be there. The range mentioned is to guarantee all chips can work in this range across PVT corners.
The following is our example PLL core beh model and a simple TB to drive and check this PLL core. The PLL core beh model is an example but to show how a PLL model delivered by analog team may look at.

Waveform is as below.





PllTb.v and Pll.v are here:


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