I have been dealing with an annoying yet interesting issue for a while. A design works perfect at RTL level. I mean no sim issue. But once it is put on Xilinx FPGAs, depending on FPGA types, some FPGAs exhibit weird behavior which can not be explained with RTL design at all. Even worse is with the same FPGA type, if synthesis constraint is changed, sometimes this weird behavior can also show up.
Yes, it does sound like a timing issue. But timing report is clean. End of day when it is root caused, it turns out to be related to combinational logic glitch or reconvergence. By reconvergence, I mean something like below. A signal, called “in”, goes through two different paths, A and B, and eventually drives the same output “out”.
Let’s dive into details.
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