Here let’s check out an interesting asynchronous interface design without a synchronizer. We use APB bus as an example but the design methodology is applicable to other buses.
Below is a typical APB slave interface diagram. APB master drives clk (PCLK), controls and data to APB slave. APB slave uses PCLK for write and read operation. But a typical issue is if APB slave resides far away on chip from APB master and if PCLK is of high clock rate, it is difficult to close timing among this interface.
An interesting async interface design can solve this issue. Below is APB write timing with inserted wait states.
Let’s say we use below code to generate a signal, called ACLK, out of PENABLE.
always@(posedge PCLK or negedge PRESETn)
if(!PRESETn) PENABLE_d <= 1'b0;
else PENABLE_d <= PENABLE;
assign ACLK = PENABLE & ~PENABLE_d;
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