AHB to WISHBONE, WISHBONE to AHB, and AHB to PCI Bridges in Verilog

Make it to the Right and Larger Audience

Blog

AHB to WISHBONE, WISHBONE to AHB, and AHB to PCI Bridges in Verilog

 

Many IPs on Opencores.org use WISHBONE bus. Opencores provides AHB to WISHBONE and WISHBONE to AHB protocol conversion designs. Here is a similar solution.

AHB single read/write transaction is

ahb_wb1

 

WISHBONE single read/write transaction is

ahb_wb2

 

Comparing these two, we can see AHB separates address phase with data phase while WISHBONE keeps address and data valid at the same time.
AHB burst read/write transaction is

ahb_wb4

 

WISHBONE burst read/write transaction is

ahb_wb5

 

Out of above two, we can get the same observation that AHB separates address phase with data phase while WISHBONE keeps address and data valid at the same time.
An AHB to WISHBONE bridge diagram is

ahb_wb6

 

The corresponding Verilog code is

A WISHBONE to AHB bridge diagram is

ahb_wb7

 

The corresponding Verilog code is

As a bonus, here is an AHB to PCI bridge Verilog code:

 

 
Engineer
Author brief is empty
Groups:

1 Comment
  1. hollis 5 years ago
    0
    -0

    Wishbone is not popular as AMBA dominates in SoC. Many IPs on opencores use wishbone so these bridges come in handy. But if you can, I’d say you may want to replace wishbone with AMBA totally especially for burst operation.

    0

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2021  ValPont.com

Forgot your details?