AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code

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AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code

Ram inside FPGA is convenient to use but is costly. If your FPGA based design needs a large memory to buffer data, you are better off using external memories on board. Popular memories are SDR SDRAM and DDR SDRAM for their large capacity, low cost, and high speed/performance. Using SDRAM is not trivial. Taking SDR SDRAM for example, you need to initialize before access and you also need to take care of refresh, various delays, and burst access to enhance the throughput. Sometimes we use external RAM for their ease of use and very high speed but they normally come with a much smaller capacity compared to that of SDRAM and are very costly (normalized to bit) so they are not a good choice for large data buffering.Synchronous RAM is normally preferred since asynchronous ram timing can be a nightmare and often designer needs to put in lots of margin for it to work across temp and voltage.
Let’s say we have the following design. We have a data producer module which needs to send data to data consumer module. We’d like to have data buffer sitting in the middle because data coming in from producer module is in small chunks and chunk order is random. We need to align the chunks properly in data buffer. Therefore when data consumer module reads data out of data buffer, data is in order.

sdram_1

To ease design, we can use ping-pong buffer so when producer is writing data into one buffer, consumer can read data out of the other buffer. Control unit module coordinates the process by controls the behaviors of data producer and data consumer modules and it also gets status information from two data modules. Note control unit also writes some control information into the proper location in data buffer so the data that data consumer reads out has not only data chunks aligned but also control information aligned with data. All digital blocks are inside FPGA while two SDRAMs are external.

There are a variety of ways to implement this design. We use bus based design as below. The bus we select is the popular ARM AHB bus. As can be seen, we have a bus matrix which consists of three master input ports and four slave output ports.

sdram_2

 

AHB bus matrix is inter-connect module for AHB bus which allows multiple masters to access multiple slaves. Its architecture is as below. Master input ports are connected to AHB bus masters which initiate read or write transactions. Slave output ports are connected to AHB bus slaves which respond to read or write transactions. Bus matrix has built-in arbiter on each output stage since multiple masters may access a slave at the same time.

ahb_bus_matrix

 

Going back to our design, data producer and data consumer module each has a master port because they need to initiate write and read transaction, respectively. Control unit has a master port to control data producer and data consumer and also write control information into data buffers (two SDRAMs). Note data producer and data consumer module each also has a slave port so control unit can access them. We also have AHB SDRAM controller module to convert AHB access to SDRAM access and maintain SDRAM data integrity.
The short-coming of this implementation is the throughput. AHB bus matrix likely limits the highest clock rate you can run. But in our design, speed is not a concern and the flexibility is the top requirement so we choose this bus based design.
There are some online resources about how to design SDRAM controller. Here we provide the Verilog code for our AHB SDRAM controller.

Zip file:

.ahb_sdrctrl.zip

 

 
We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.
1 Comment
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    JLee 5 years ago
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    -0

    Interesting. Assume writing data into one sdram and reading data out of the other sdram occur in parallel. Shall we use split bus matrix to improve throughput?

    4

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