Xilinx chipscope is a heavily used FPGA debugging tool. Its ILA core allows user to tap into internal signals of RTL design and check how they toggle with the support of various trigger conditions.

Chipscope and its ILA is not available to SOC. On SOC a typical debugging approach is to wire internal signals to debug bus and then route debug bus to SOC pins. Lots of cases this is a good enough solution. But its limitation is obvious. SOC is normally pin limited. Even with multiple signal time-multiplexing used, pin usage by debug bus is low which means a pin is dedicated to one or a few signals while there could be many other signals not shown.

If we look into how ILA works, we notice ILA doesn’t route internal signals to pins and instead it dumps internal signals to internal memory and then use JTAG to read out memory and display on your screen. Pay attention to “Data Capture Memory” block in the following diagram.

The reason Xilinx implements ILA in such way is obvious. Internal signals could run at very high speed, like several hundred of Mhz. But JTAG is slow and about 10Mhz. So no way to dump internal signals to PC real time. So dump to internal mem first and then use jtag to read it out off-line. This approach can be applied to SOC as well to do the so-called hardware logging.

 

RTL FE Design Team in SD

We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.