I needed to design a flexible fractional clock divider. Never did it before so I started from scratch. Later I found Larson has a good fractional clock divider design posted on this site, A Flexible Digital Fractional Clock Divider with Verilog Code. It is simpler in design and easier to be controlled. But I still would like to share my design in this community in case someone is interested in it.
Let’s say we want to generate a 20Mhz clock out of a 35.5Mhz clock. This 20Mhz is on average and has to be with varied duty cycles. My idea is to pass 35.5Mhz clk for some time and block it for some time. This idea is illustrated in below timing diagram. I run a counter which increments on clk_in. When the counter value is from 0 to M (programmable), we pass clk_in to clk_out. When counter value is from M+1 to N (programmable), we block clk_in to clk_out. Counter restarts from 0 when counter reaches N.
Next we can determine M and N for our 35.5Mhz/20Mhz example. The equation is M=N*20Mhz/35.5Mhz. So we can select N=355 and M=200. But it means clk_out toggles for 200 cycles and then idle for a LONG (355-200) cycles. We can do better than this. We can select N=71 and M=40 so clk_out is only idle for 31 cycles.
But we can do even better. Let’s say clk_out only toggles for two cycles and then idle for a long time.
We can spread clk_out toggles. Instead of allowing it toggle every cycle for the passing window, we can let it toggle for some cycles and stop for some cycles and repeat. In below diagram, during passing window we let it toggle for one cycle and stop for one cycle and then repeat.
Firmware can program:
- N which is passing window plus blocking window
- M which is passing window
- Pattern in passing window. Pass for how many cycles and stop for how many cycles.