A Scalable Verilog Testbench II: full workable code and scripts

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A Scalable Verilog Testbench II: full workable code and scripts

This is a follow up to previous post of “A Scalable Verilog testbench to support multiple test cases”. The attachedĀ tarball of this post contains all the workable rtl, tb, and scripts. Here is how it works:

  1. download and untarĀ theĀ attached file.Ā All files are in /example dir. Place /example under your $HOME.
  2. go to $HOME/example/scripts and run “source setup.sh”.
  3. create your sim directory anywhere, for example $HOME/sim.
  4. go to $HOME/sim, run “create_tests.pl”. it will create two test cases/folders, test1 and test2. It will also compile common rtl files into common lib atĀ $HOME/sim/clib.
  5. at $HOME/sim, run “run_tests.pl”. it will run test1 and test2 one by one and dump waveform vsim.wlf into each test case directory.


Here I am using Modelsim as sim tool. No particular requirement on Modelsim version as long as commands such as vlog and vsim can be found. The test bench and script can be easily ported to other sim tools.

You can also refer to previous post for the ideas behind this test bench.


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  1. ramin122002 4 years ago

    Thank you very nice

  2. tDey 4 years ago

    Just what I am looking for. A full rtl and testbench setup with all scripts and sample code.


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