Need a flexible digital fractional clock divider in design. Note it is not PLL based clock divider. Need a simple and all digital solution. Requirements are:

1. The fractional divider is flexible. Hopefully just N/M.

2. Due to fractional nature, it is expected output clk cycles will vary. But the variation should be as minimum as possible. In other words, let’s say we want to get 10/3=3.333 divider and assume input clock cycle is T. Then output clk cycle should be just 3T and 4T and we should have two 3T cycles and one 4T cycle alternate so on average the output clock cycle is (2*3T+4T)/3=3.333T.

3. Clock duty cycle is as close to 50% as possible. Taking above as an example, the 4T clock cycle should be 2T in low state and 2T in high state instead of 1L/3H or 1H/3L.

Searched web. There are several articles talking about fractional clock divider. For example:

Design for realizing arbitrary fractional divider

Programmable Fractional Clock Frequency Divider Circuit

But they are not exactly what I am looking for. After some study, looks a simple fractional clock divider can be as below.

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I have implemented a design exactly like that back in 2013 at a company I used to work at at that time. We called in the N/R divider, with R = 2^K – M.

Full disclosure: I copied the Verilog code from a paper I got from a coworker. But I can swear that code of our clk_div.v looked like an exact copy of yours. Would you mind sharing your source?

You are late. I was told similar design was seen back in around 2006.

Since clock cycle varies, we use the min clock cycle to set constraint?

I would say so.

Good article and very practical and useful design. Sure I can apply this in my next design.