A DDR3 PCB Design Case Study

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A DDR3 PCB Design Case Study

Worked on PCB design with DDR3. Found a very useful DDR3 PCB design guide from Freescale. This app note not only answers my questions but also gives many potential issues and solutions that I didn’t foresee.

A common question about DDR3 routing is trace length matching. Here is what the app note says:

The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate.
An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing. When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the tDQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves.

So data signals are not length matched to clocks but to the respective data strobe and data mask signals. The doc suggests each data lane should be trace matched to within 20 mils of its respective differential data strobe and data lanes should be matched to within 1 inch.

In my case, I have two DDR3 SDRAMs and for a 32bit word one DDR3 provides lower 16bit data and the other provides upper 16bit data. So I have clock, address lines, etc. going from micro-controller to each SDRAM. In PCB layout, I placed two DDR3 close to each other and also close to micro-controller with the same distance. But note some space among three components were reserved to route signals.


The app note says do not route any DDR3 signals over splits or voids and ensure traces routed near the edge of a reference plane maintains at least 30-40 mil gap to the edge of the reference plane. This is strictly followed in routing. Indeed, data signals are routed on layer 9 which is adjacent to ground layer 10 and addresses are routed on layer 8 which is adjacent to ground layer 7. We try to make layer 9 and layer 8 routing vertical to each other as much as possible since they are adjacent layers. In addition, we avoided signal routing across multiple layers as much as possible which is also suggested by the app note.





Out of above two pictures, you can also see many serpentine loops to do length matching. The app note says to ensure at least 25 mils between serpentine loops in parallel. We didn’t have much real estimate on board and we ended up with about 19 mil spacing between serpentine loops.


About trace width and spaing, the app note says:

Choose one of the following options to select the impedances and spacings for the DDR3 data group.
Option #1 (wider traces—lower trace impedance)
• Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly closer with less
• Utilize wider traces if stackup allows (7–8 mils)
• Spacing to other data signals = 1.5x to 2.0x
• Spacing to all other non-DDR signals = 4x
Option #2 (smaller traces—higher trace impedance)
• Single-ended impedance = 50 Ω.
• Smaller trace widths (5–6 mil) can be used.
• Spacing between like signals should increase to 3x (for 5 mil) or 2.5x (for 6 mil) respectively

In our routing, we used 3.2mil for trace width and we followed 3W rule so trace spacing was 10.5mil. When you route, better to simulate how much impedance it is. There are many tools to do so. You can conveniently use this one at Valpont, http://www.valpont.com/tool-spreadsheet-to-calculate-trace-impedence-and-propagation-delay/pst/

Go to stripline sheet. We used dielectric constant 4.6, dielect thickness 7 mil, trace width 3.2mil, and trace height 1.4mil. We got about 55.95ohm for the impedance. We were not very sure of trace height T. So we also tried 1mil and 1.8mil, impedance varies from 58.2ohm to 53.98ohm which are acceptable.

Since we have two DDR3, differential clock signals and other signals such as addresses, cs, we, odt, and ba all take Y shape on board. We simulated to to make sure the trace impedance is continuous at the Y split to avoid any signal integrity issue.
Here is the app note, http://cache.freescale.com/files/32bit/doc/app_note/AN3940.pdf

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