Clock switching is commonly used in ASIC and FPGA design. Rafey Mahmud had an article talking about glitch free clock switching at: http://www.eetimes.com/document.asp?doc_id=1202359
The circuit proposed is as below:
Inspired by this circuit, a similar glitch free clock switching circuit can be as below:
First, ICG cell is used. In lots of ASIC design projects, ICG cell is normally given which consists of a D flip-flop with inverted clock and an AND gate as shown in above dashed box. (I am using Digikey Schemeit to draw the circuit but the tool doesn’t have symbol for DFF with inv clock so I use inverter+DFF). ICG’s clock enable input needs to be in the SAME clock domain as the clock otherwise the gated clock out can be glitchy.
Second, using two FF’s to form a clean synchronizer.
Above circuit works like this. When power is applied and reset is asserted, all FF out is 0 and two ICG cells gate off clk0 and clk1. When reset is removed, let’s say select=0, the AND gate before clk0 synchronizer outputs 1 because two AND gate inputs are inverted select (=1) and enb1 (=1). Note select and enb1 are not in clk0 domain so AND gate output can not drive ICG cell directly and we need to use synchronizer. After two clk0 cycles, synchronizer passes 1 to clk0 ICG and turns on clk0 .
When select becomes 1, enb0=0 will hold clk1 turned off. enb1=1 will pass select to turn off clk0. When clk0 is off, enb0 becomes 1 and this will turn on clk1 path. As can be seen, the key idea to do glitch free clock switching is to turn off one clock before turning on the other one.
Actually above circuit is flawed or has limitation. When select goes from 0 to 1 and enb0 goes from 0 to 1 too, it takes half clk0 cycle for clk0 ICG to turn off clk0 while it takes 2.5 clk1 cycles for clk1 path to turn on clk1. So if clk1 rate is 2.5x higher than clk0, the circuit fails. To resolve it, we can add one clk delay on enb0 and enb1 as below:
Finally, the above 2×1 clock switching can be easily extended to Nx1 case. As can be seen from below circuit, first we need a one-hot encoder on select so at one time only one path gets turned on. Second, the AND gate before each clk path takes in enb (or enb_dly) from each clock path other than itself. So this clock is turned on AFTER all the other clocks are turned off.
Trydeman posts two issues about this glitch free clk switching circuit at Two Potential Issues with Glitch Free Clock Muxing Good thinking. Both issues are valid.
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