UPF Example and Using UPF in Real Silicon Design

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UPF Example and Using UPF in Real Silicon Design

Low power digital design with multiple power and voltage domains has become indispensable in most modern ASIC designs. IEEE 1801 (UPF) is widely adopted as industry standard to specify, verify and implement power intent. UPF has two main usages, UPF for design and verification team to run power simulation and UPF for Backend team to implement power intet such as connect power, add isolation, etc. These two usages are related but separated. For example, some projects may only use UPF for power simulation and Backend team still uses non-UPF flow to take care of power. With the benefits of UPF flow presents, it is preferred for both design/verification team and Backend team to adopt UPF flow. Reason is simple – the same UPF passing low power simulation is also used for Backend process so it is less likely to make mistake or mis-communicate. Note in reality UPF file for BE and UPF file for simulation will be a little bit different. Sometimes it is due to different tools used so some syntax need to be changed to fit the tool.

Before UPF simulation, how do we simulate low power design? First, for low power controller, you can run regular RTL simulation to check the waveform although control signal doesn’t really turn off power so simulation doesn’t fully reflect the real case. There are some tools that allow you to specify if some control signal is asserted then all FFs in some module goes to ‘x’. Pretty much this is also what UPF does in sim. Second, BE PAR (place and routing) tool can generate two kinds of netlists, with and without power information. The one without power information is the regular netlist that you use to run gate simulation. The one with power information such as supply connection, power switch, etc., is called power aware netlist. Running simulation on this netlist is slower so lots of times we only run a small set of test cases, normally low power test cases, against it.
Let’s go back to UPF flow and take a look of a simple example.

upf_1

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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and FPGA digital design. We successfully led several chips through the whole process from feature define, RTL design, verification, to backend/DFT support, TO, and bring-up. We are familiar with Xilinx FPGA design too and have experience in using multiple FPGAs to verify complicated ASIC RTL design or for the final product. We are interested in working as independent contractor for your projects. Please send us private message if there is a match. Thank you!
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1 Comment
  1. Ltremblay 2 years ago
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    Thanks “RTL Team”. Great introduction about UPF and very practical example and related UPF code. Plus the very interesting power division introduced signal deadlock issue.

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