UPF and Retention

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UPF and Retention

This post is intended for low power design starters and answer some basic questions:

  1. retention flip flop is supposed to hold flip flop content. why do I see ret FF outputs becomes ‘x’ in sim in retention mode?
  2. when ret FF output is out of ‘x’? is it when main pwr is re-applied or when retention condition (specified in UPF) is not met?
  3. I have a power supply net which is partial on. Does it cause retention FF to loose its content?
  4. How can I change my power supply net to be full on?
  5. What is relationship between supply set is NORMAL or CORRUPT and supply net is full_on, partial_on, off, etc?

 

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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and FPGA digital design. We successfully led several chips through the whole process from feature define, RTL design, verification, to backend/DFT support, TO, and bring-up. We are familiar with Xilinx FPGA design too and have experience in using multiple FPGAs to verify complicated ASIC RTL design or for the final product. We are interested in working as independent contractor for your projects. Please send us private message if there is a match. Thank you!
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1 Comment
  1. DRama 2 months ago
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    Good explaining

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