# [Tool] PCB Via Capacitance and Inductance

Make it to the Right and Larger Audience

Blog

# [Tool] PCB Via Capacitance and Inductance

Via is predominantly capacitive. Its capacitance increases signal rise and fall time and therefore reduce board speed.

Via’s capacitance can be expressed as
$C_{via}=1.41\epsilon_rTD1/(D2-D1)$

where D2 is the anti-pad diameter in inch, D1 is the via pad diameter in inch, T is the via height and in lots of cases the same as the thickness of the PCB board, and $\epsilon_r$ is the relative dielectric constant of the board material.

For example, if PCB board thickness is 50mil, anti-pad diameter is 40mil, pad diameter is 20mil (drill hole diameter 10mil), we can use above equation to calculate via capacitance as 0.31pF. Then the extra rise time it can cause is:
T10-90=2.2C(Z0/2)=2.2*0.31*(50/2)=17.05ps

So a single via effect is not much. But if you have multiple via on a trace and if the trace is for a high speed signal, it can cause severe signal integrity issue. To reduce via capacitance, as indicated in equation, you can increase anti-pad area size (increase the distance between via and copper area) or reduce pad size.
In addition to capacitance, via can also introduce inductance. This inductance can cause more signal integrity issue than via capacitance in many cases. For example it can offset the effect of decoupling capacitor.

Via inductance can be expressed as
$L_{via} = 5.08h(ln(4h/d)+1)$
where h is the via height and d is the drilling hole diameter. This equation does not take into account current return path. If there is a nearby via which is grounded, via inductance can be reduced. Compared to drilling hole diameter, via height contributes more to inductance. For example, if via height is 50mil and drilling hole diameter is 10mil, L is 1.015nH. If a signal’s rise time is 1ns, the bandwidth (Ghz) of this signal can be give as 0.35/RT(ns)=0.35Ghz. At this frequency, the impedance introduced by this via inductance is 2.23ohm. This impedance can not be ignored in high speed signal analysis. In addition, decoupling capacitor routing needs two via, one for power and one for ground, so the effect of via doubles.
Here are some tips when using via:

1. Determine via size from both the cost and signal integrity point of view. You may consider to use via of different sizes if necessary. For example, larger via for power and ground and smaller via for signals.
2. Reduce the thickness of board can reduce both via capacitance and inductance.
3. Optimize signal routing and remove unnecessary via.
4. Put via close to power and ground pins. Use multiple via to reduce equivalent inductance.
5. Put grounded via close to signal via to introduce return current path to reduce via inductance.
6. Use micro-via for high speed boards.
Below is xls calculator for your convenience.

Freelancer at Freelancer
Author brief is empty
Groups:

Tags:

## pcbvia

1. KSen 5 months ago
0
-0

4
2. bencouto 2 years ago
0
-0

Nice quick analysis without running sum tools.

5
3. stsai 2 years ago
0
-0

Just a note that the equation to calculate cap assumes there is a ground barrow around via hole so it normally over estimate capacitance. But board design needs margin so a good first order estimation for most projects

4
4. wells010 2 years ago
0
-0

Good article.
Just want to add via is not always bad to SI and EMI. One example is the so-called via stitching to reduce EMI emission.

5
5. RaviD 2 years ago
0
-0

Nice tips on using via.
There is a good discussion about via inductance from Dr. Johnson, the author of the famous SI book “high-speed digital design”. Good reading if you want to explore more.
http://www.sigcon.com/Pubs/news/6_04.htm

5