Timing and Clock, How DFT and BE can Mess up your Design

Make it to the Right and Larger Audience

Blog

Timing and Clock, How DFT and BE can Mess up your Design

One big problem between frondend team and backend team is miscommunication. For example, to cut down power consumption, frondend team comes up a design with multiple clock domains as shown in below. Each clock domain can run at its own clock rate, as slow as possible. Even they run at the same clock rate, they are still asynchronous to each other to cut down the power and ease timing closure.

So far so good. Next we will see how BE timing constraint and DFT can mess up this asynchronously well partitioned design.

 

 

The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 962 words, 6 images
 
Consultant at Freelancer
I am a digital IC backend expert with 10+ years of DC, PTPX, DFT, and layout experience. I am open to backend service. Please ping me if you're interested.
Groups:

Tags:

0 Comments

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2018  ValPont.com

Forgot your details?