Reset ARM subsystem in Single Core and Multiple Core System May Not be Easy

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Reset ARM subsystem in Single Core and Multiple Core System May Not be Easy

 

Below is a simplified ARM subsystem typically seen in a low power SoC design for embedded and IoT applications. We have a Cortex-M processor and DMA as AHB bus masters and three function modules as AHB bus slaves. AHB masters and slaves are inter-connected through ARM AHB bus matrix module. We will start with this simple single core case. As will be seen, reset of this simple system is not straightforward.

 

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