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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and FPGA digital design. We successfully led several chips through the whole process from feature define, RTL design, verification, to backend/DFT support, TO, and bring-up. We are familiar with Xilinx FPGA design too and have experience in using multiple FPGAs to verify complicated ASIC RTL design or for the final product.
Feel free to check our blogs and articles. Let us know your questions and we are willing to help!
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