Power Supply Connection in Low Power Design

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Power Supply Connection in Low Power Design

Low power is critical in today’s ASIC design. This post dives into considerations and issues of power supply connection in low power design.

Below is a typical retention FF. SPRG here means state retention power gating. Notice this retention FF has two power supplies, VDD and VRET. In normal mode, both VDD and VRET are on and of the same voltage level. As a matter of they also consume the same current. In low power (aka sleep) mode, VDD is off and VRET is on to keep FF content. The right side waveform shows the timing sequence of entering and exiting sleep. For entrance, first gate off clock, then assert retention ctrl, then VDD can be removed.

One more word is FF is often of master-slave type. VDD powers master latch and the output stage of FF. VRET powers slave latch. In sleep mode, only slave latch gets power.

All good. But this is likely not what is implemented in real silicon. This will be explained later. It is related to the main subject, how power source is connected.

Sram low power is a big topic due to considerable memory power consumption in both normal and sleep mode. Below shows an example of a sram design with low power in consideration. The diagram is a little busy. Key point is this sram has two power domains, VCORE and VCELL. VCELL powers memory array cells and VCORE powers the control logics. To lower power, each power domain can be powered off. In sleep mode, we may want to keep the content of sram. In this case VCORE is off and VCELL needs to be on. Otherwise both can be off.

As in retention FF case, a question to be answered is how to connect power supplies to VCORE and VCELL. What are considerations and potential issues.

A broaden question is how to connect power supplies to non-retention FFs, power gated off logics, and AON logics.

 

First we need to get prepared what power supplies are normally available in today’s ASIC chips.

The PMU, power management unit, can be quite complicated. Two common power sources are LDO (low dropout regulator) and SR (switching regulator). In a complicated ASIC design like LTE modem plus AP processor, PMU can easily contain over 100 LDOs and SRs. Below is a typical LDO block diagram.

The pro of LDO is low noise and the con is low efficiency. Its power efficiency is output-voltage-level/input-voltage-level. So if the delta is large, efficiency is low.

 

The other common power supply is switching regulator. Simply speaking, it is just the opposite of LDO. High noise but high efficiency. Its efficiency can be as high as 80-90%. Below is a simplified SR diagram.

Here is how it works. Basically the inductor keeps charging and discharging. So output goes up and down around the mean value, aka output level.

One important fact about SR is its efficiency is based on load current. SR has some quiescent current. If load current is small, its efficiency will drop and quiescent current just makes efficiency worst. The high efficiency is achieved with high load current.  This is important in our next discussion of power supply selection and connection.

About high noise, a so-so designed SR can not power digital circuit directly. SR output is connected a LDO which will filter out noise and power digital logic. Obviously it is not ideal since extra LDO means extra design-test-effort/area/cost and also extra power consumption. A fine tuned SR design can power digital circuit directly but may be still not good enough to power analog/RF circuit and therefore a LDO is needed.

 

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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.
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