PCIE Tutorial: Software Initiated Device Power Management

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PCIE Tutorial: Software Initiated Device Power Management

PCIE supports four device power states, D0, D1, D2, and D3. D0 is mandatory and is full-on state. D0 has D0 uninitialized and D0 active two sub-states. D1 and D2 are optional. D1 is light sleep and D2 is deep sleep. D3 is mandatory and is the lowest device power state. D3 is full-off state and has D3cold and D3hot two sub-states.

During enumeration, system software will read capability register sets of device. Lower 8bit of DW#13 in config space is the capability pointer. It points to the 1st set of capability registers. Bit15 to 8 of the 1st capability register is the pointer pointing to the next one. For power management capability register, capability ID, lower 8bit of the 1st DW, is 01h which indicates it is power management capability register set.

Bit31 to 16 of the 1st DW is PMC, power management capabilities. This is determined by device design. At enumeration, system software reads this 16bit to know device PM capability. Inside PMC, [2:0] is version. [3] is PME clock. [3]=1 indicates pcie refclk is needed by device to generate PME. [9] is D1_support. [9]=1 indicates device supports D1. Strictly speaking we should say [9]=1 indicates FUNCTION supports D1. This is because a pcie device may have multiple functions. [10] is D2_support. [10]=1 indicates function supports D2. [15:11] is PME_support indicating in which power states the function can send a PME message. Bit[15:11] correspond to D3cold, D3hot, D2, D1, and D0 state.

After system software, aka, system driver, reads PMC, it can program [1:0] of PMCSR to put function into different power states. Driver can also read PMCSR[1:0] to know the device state status. Driver can program PMCSR[2]=1 to enable function to generate PME#. PMCSR[15] is PME_status bit and driver reads this bit to query function PME event status (will be explained later).

Below is device state transition diagram. So system driver can put device into various power states. But it is really up to the device how to implement these power states. For example, a cellular modem device may just keep radio, modem, mac all on even in lowest D3cold power state. Overall pcie is just a communicate channel/link between system and device. What device power states directly controlled is the pcie link power. In the next, we will talk about pcie link state and use two examples to show how D2/L1 and D3/L2L3 work.

 

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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and FPGA digital design. We successfully led several chips through the whole process from feature define, RTL design, verification, to backend/DFT support, TO, and bring-up. We are familiar with Xilinx FPGA design too and have experience in using multiple FPGAs to verify complicated ASIC RTL design or for the final product. We are interested in working as independent contractor for your projects. Please send us private message if there is a match. Thank you!
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