Make it to the Right and Larger Audience
Verification, UVM, RTL, FPGA
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tDey posted in IoT and Smart Devices 2 weeks, 5 days ago · , 0, 1
IOT to be excited and worried in 2018
Four reasons to be excited
It’s easier than ever to build IoT devices
IoT platforms have dramatically lowered the barrier to entry
IoT big data analysis is becoming more accessible
IoT security is gaining traction
Four reasons to be worried
Few IoT…[Read more]
tDey posted in IoT and Smart Devices 1 month, 2 weeks ago · , 1, 2
Small tracing sensors with a mobile app, neat product and plenty of use cases?
tDey posted an update 1 year, 3 months ago · , 0, 0
Verilog: range must be bounded by a constant expression
Lets say you want to achieve below in verilog
for(int ind=0; ind<8, ind++) begin
target[32*(ind+1)-1:32*ind] = source[31:0];
Compilation will fail with error msg as "range must be bounded by a constant expression". You can use…[Read more]
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tDey commented on the post, A Scalable Verilog Testbench II: full workable code and scripts 1 year, 3 months ago · , 0, 0
Just what I am looking for. A full rtl and testbench setup with all scripts and sample code.
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