No polls to show


  • tDey posted an update 1 year ago · , 0, 0

    Verilog: range must be bounded by a constant expression

    Lets say you want to achieve below in verilog
    for(int ind=0; ind<8, ind++) begin
    target[32*(ind+1)-1:32*ind] = source[31:0];
    end

    Compilation will fail with error msg as "range must be bounded by a constant expression". You can use…[Read more]


There was no activity posted yet.