Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.
“Most people have tried to use asynchronous technology to compete with Intel or Nvidia at the high end, routing gigahertz clock trees or designing deep-learning accelerators. We went the other way and rode voltage levels down”